1. Field of the Invention
The present invention relates generally to integrated circuits, and more specifically to a hierarchical bitline memory architecture.
2. Description of the Prior Art
In recent years, high density memories such as SRAMs, DRAMs, EPROMs, and EEPROMs have dramatically increased the level of bitline capacitance which must be driven by memory cells in the memory array. As high speed memories have increased in density, efforts have been made to carefully partition the memory array to reduce the burden on the memory cell for driving large bitline capacitances. For example, memory arrays have gone to four times the number of columns as rows to reduce bitline capacitance. In addition, the rows are sometimes bisected by the sensing and column decode circuitry to further reduce bitline capacitance. In spite of the advances made in careful partitioning of the memory array, bitline capacitance can still be prohibitively large, having an adverse affect on device speed and signal integrity. As a result, better methods for reducing the bitline capacitance as seen by memory cells while using minimum layout area are needed and appropriate.